Testing in two-dimensional iterative logic arrays

On the testability of iterative logic arrays

The problem of detecting single cellular faults in arbitrarily large one-dimensional, unilateral, combi-national iterative logic arrays (= ILAs) is considered. Fault patterns (= FPs) of the ILA's basic cell are introduced to characterize any cellular fault. Testability properties like (full, partial) testability, redundancy, test complexity of FPs are studied. Based on this analysis we prove th...

Efficient Built-In Self-Test Techniques for Sequential Fault Testing of Iterative Logic Arrays

In today’s nanometer technology era, more sophicated defect mechanisms might exist in the manufactured integrated circuits which are not covered by traditional fault models. In order to ascertain the quality of shipped chips, more realistic fault models should be addressed. In this paper, we propose built-in self-test (BIST) techniques for iterative logic arrays (ILAs) based on realistic sequen...

Chapter 17 Iterative Logic Array Testing

Iterative Exhaustive Pattern Generation for Logic Testing

Exhaustive pattern logic testing schemes provide all possible input patterns with respect to an output in the set of test patterns. This paper is concerned with the problem that arises when this is to be done simultaneously with respect to a number of outputs, using a single test set. More specijically, in this paper we describe an iterative procedure for generating a test set consisting of ndi...

Testability of AND-EXOR Based Iterative Logic Arrays

— Iterative Logic Arrays (ILAs) are ideal as VLSI subsystems because of their regular structure and it's close resemblance with FPGAs (Field Programmable Gate Arrays). AND-EXOR based circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is of much consideration. This paper examines the testability of AND-EXOR based Iterative Logi...